The present disclosure relates to timing recovery circuits, and more particularly, to a timing recovery circuit which can handle a broader band.
For example, when devices connected to a network perform data communication with each other, the clock of the receiver device is often not synchronous with the clock of the transmitter device, and in addition, the clocks often do not have the same frequency, because of a difference in an operating environment, such as power supply noise, temperature, etc. Therefore, in order to allow for data communication between these devices, the receiver device needs to perform a synchronization process based on received data. This process is commonly called “timing recovery,” “clock data recovery,” etc.
In typical timing recovery, the receiver generates a clock for receiving data, detects a phase difference between the clock and received data, and adjusts the phase of the clock based on the detected phase difference to generate a clock having a phase suitable for reception of data. As the transmission rate of data increases, it is more difficult to accurately detect the phase difference between the data and the clock. Therefore, typically, in timing recovery which can handle a high transmission rate, 1-bit data is sampled in synchronization with a plurality of clocks having different phases (this process is called “oversampling”). By detecting changes in values of data sampled according to the clocks, differences between the phase of data and the phases of the clocks are determined. A clock phase control is performed based on the differences.
Typically, an interpolator is used for a phase control. The interpolator generates a clock having an intermediate phase between the phases of two reference clocks. Therefore, the interpolator is advantageous in generating clocks having any phases based on a few reference clocks, instead of previously preparing a large number of clocks having different phases.
As the speed of data communication has in recent years been increased, there has been a demand for an interface for a broader band. For example, a digital video signal interface such as high-definition multimedia interface (HDMI) needs to handle a considerably wide range of transmission rates because the transmission rate may range from several hundred Mbps to several Gbps, depending on the number of pixels or color depth of a display device. If timing recovery is implemented by phase determination employing oversampling and a phase control employing an interpolator, the timing recovery can work properly when the transmission rate is high. However, in general, it is disadvantageously difficult to obtain an output clock having a desired phase using an interpolator when the frequency of the reference clock is low.
In order to provide a broader-band interface, it is necessary to ensure accurate timing recovery in a low frequency region as well. Japanese Unexamined Patent Publication No. 2011-97314 describes timing recovery which can handle a broadband by broadening the operating range of an interpolator. In the technique of Japanese Unexamined Patent Publication No. 2011-97314, the slew rate of a reference clock is controlled by changing the on-resistance of a pass gate transistor. Specifically, when the clock frequency is high, the on-resistance is reduced. Conversely, when the clock frequency is low, the on-resistance is increased. As a result, the operating range of the interpolator is broadened.
However, in the technique of Japanese Unexamined Patent Publication No. 2011-97314, it is difficult to provide an interface which can handle frequencies which differ from each other by a factor of 10-100. Such an interface has in recent years been demanded.
FIG. 14 is a diagram showing a configuration of a conventional timing recovery circuit (see, for example, Japanese Unexamined Patent Publication No. 2009-239768). This timing recovery circuit can handle a broader band by dividing the frequency of an output clock of an interpolator instead of broadening the operating range of an interpolator itself.
Specifically, a PLL 801 outputs multiple-phase clocks Mulclk having a frequency which is constant irrespective of the transmission rate of data. An interpolator 802 generates a clock Compclk whose phase is set based on a phase control signal sig3 using the clocks Mulclk as a reference clock. The clock Compclk has the same frequency as that of the clocks Mulclk. A frequency division circuit 803 generates a clock Rclk having a frequency suitable for the data transmission rate. The frequency division circuit 803 performs frequency division operation in synchronization with the clock Compclk, and therefore, can reduce the frequency of the clock Rclk while maintaining the phase of the clock Compclk.
A phase determination circuit 804 compares the phases of the clock Rclk and data DATA, and outputs a signal sig1 as a result of the phase comparison. A filter 805 outputs a signal sig2 as a result of smoothing the signal sig1. A pointer circuit 806 updates the value of the phase control signal sig3 based on the signal sig2. Thus, timing recovery is achieved.
In this timing recovery circuit, it is not necessary to limit the operating range of the interpolator 802. If the frequency of the clocks Mulclk is set within the operating range of the interpolator 802, a clock having a frequency suitable for the transmission rate can be generated by only setting the frequency division ratio of the frequency division circuit 803. Therefore, timing recovery which can handle a broader frequency range can be achieved.